FIG. 1 is a conventional simulation structure for a logic circuit such as a ring oscillator. As shown in FIG. 1, the simulation structure comprises odd numbered (usually more than three) logical units 10 connected to each other in head-to-tail series. In FIG. 1, three logical units 10 form a ring oscillator. The output port of one of the logical units is electrically connected with the input port of at least one frequency divider 12. The logical unit can be an inverter, a NAND gate, or a NOR gate.
Referring to FIG. 2, which is a top view of two adjacent logical units, each of the two logical units 10 comprises a PMOS transistor and a NMOS transistor. Defined herein, “AA” refers to an active area, “poly” refers to a polysilicon gate layer, “contact” refers to a contact hole layer, “M1” refers to a metal interconnect layer, “vss” refers to a ground voltage, “vdd” refers to a power supply voltage. The output port of one logical unit is directly connected to the input port of the other logical unit through a metal connection line in the metal interconnect layer M1.
It is well known to those skilled in the art that actual ring oscillator circuit design is based on simulation results of the simulation structure. However, there exist errors between the simulation results and the actual measurement results, which affects the subsequent circuit design. Such errors are mainly caused by inaccurate device model and improper back-end-of-line (BEOL) interconnect parasitic extraction.
Nowadays, it is difficult to determine whether the errors between the simulation results and the actual measurement results are primarily caused by errors in device module or errors in BEOL interconnect parasitic extraction. Conventionally, the errors in the simulation results are compensated by adjusting a capacitance value in the device model, assuming the errors in the BEOL interconnect parasitic extraction to be zero. Such compensation method fails to determine the actual cause of the simulation error, which may result in both inaccurate device model and inaccurate BEOL model. Accordingly, logical circuit design based on these inaccurate models will not meet expectation.
From above, determination of device model error or BEOL interconnect parasitic extraction error is the key to reduce circuit simulation errors, and is a pressing problem to be solved.